ASM5I9658
Key Features
- Both must be selected to match the VCO frequency range
- The internal VCO of the ASM5I9658 is running at either 2x or 4x of the reference clock frequency
- The ASM5I9658 has a differential LVPECL reference input along with an external feedback input
- The ASM5I9658 is ideal for use as a zero delay, low skew fanout buffer
- The device performance has been tuned and optimized for zero delay performance
- The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis
- The PLL bypass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply
- The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin
- Asserting MR/OE also causes the PLL to loose lock due to missing feedback signal presence at FB_IN
- Deasserting MR/OE will enable the outputs and close the phase locked loop, enabling the PLL to recover to normal operation
